Inverter and like circuits employing transistors



'r. H. BROWN 3,012,205 INVERTER AND LIKE CIRCUITS EMPLOYING TRANSISTORS Dec. 5, 1961 Filed Jan. 31, 1958 fi fi o D lim E A m R C m R P M l\ w C1 o A Nll F m 0 TU! .A I m I. 2 II P R H. w L L A Ill Io ALL COILS ARE ON A COMMON CORE FIG. 2

INVENTOR THOMAS PNRY BROWN .ziw A AGEN United States Patent ()filice 3,012,205 Patented Dec. 5, 1961 3,612,205 INVERTER AND LIKE CIRCUITS EMPLUYING TRANSISTORS Thomas Henry Brown, Old Coulsdon, England, asslgnor to North American Philips Company, Inc, New York,

' Filed Jan. 31, 1958, Ser. No. 712,414

4 Claims. (Cl. 331--109) This invention relates to inverter and like circuits employing transistors.

Such circuits may be used as inverters proper to give an A.C. output or they may be used in so-called D.C. converters in which the alternating output is rectified for use as a D.C. output, usually of higher voltage than the DC. input.

In many transistor inverter circuits there is a danger of excessive power dissipation in the transistors occurring as a result of a short-circuit across the load or other abnormal increase in the load current.

It is the principal object of the present invention to provide improved transistor inverter circuits capable of preventing, automatically and reliably, damage to the transistors due to such causes.

According to one aspect of the invention an inverter circuit arrangement comprises a pair of input terminals for connection to a DC. input source, a transistor in a circuit adapted to operate as an inverter to supply an output voltage to a pair of output terminals provided for connection to a load, means for monitoring the said output voltage or a voltage substantially proportional thereto, and protection means adapted to cause cessation or reduction of power dissipation in the transistor in response to departure of said voltage from a predetermined level or range of levels.

According to a further aspect of the invention, a pushpull inverter circuit arrangement comprises a pair of input terminals for connection to a DC. input source, two transistors in a circuit adapted to operate as a push-pull inverter to supply an output voltage to a pair of output terrninals provided for connection to a load, means for monitoring the said output voltage or a voltage substantially proportional thereto, and protection means adapted to cause cessation or reduction of power dissipation in the transistors in response to departure of said voltage from a predetermined level or range of levels.

The collector voltage of each transistor has preferably a substantially square Wave-form, and the monitor means may be arranged to monitor only the level of the waveform corresponding to the conducting state (ie the more positive level in the case of a p-n-p transistor). In the latter event, a push-pull inverter may employ a pair of rectifiers to provide a substantially smooth D.C. voltage corresponding to the mean value of the said voltage level for operation of the protection means. By contrast, an asymmetrical inverter circuit employing only one inverter transistor gives a monitored wave which may require considerable smoothing for use in controlling the protection means.

The monitored voltage may be compared with a predetermined reference voltage.

Each inverter transistor may be a junction transistor having connected across its emitter-base path the emittercollector path of an auxiliary transistor controlled by the protection means, said protection means being adapted to render the emitter-collector path of said auxiliary transistor highly conductive under over-load conditions.

In the case of a push-pull circuit, the inverter transistors may have their collector circuits coupled together and to the output or load terminals by a transformer. Moreover, in the case of a self-excited inverter circuit, transformer means may be used for providing feedback coupling between the emitter-collector circuit and emitterbase circuit of each inverter transistor. Embodiments of the invention employing transformer means for both these purposes will now be described by way of example with reference to the accompanying diagrammatical drawmg.

FIGURE 1 shows an already known self-excited pushpull inverter circuit to which protection means in accordance with the invention may be applied. In the circuit of FIGURE 1, p-np junction transistors T and T are alternately bottomed when the circuit is oscillating. In the bottomed condition of a transistor, power dissipation occurs at a safe level due to the very low voltage drop across the transistor. The characteristics of the transistors are such that excessive dissipation takes place if conduction is allowed to occur with the higher voltage drop conditions obtaining outside the bottoming region.

The frequency of oscillation is controlled by the saturation characteristics of the transformer core material. Elements R D connected across D.C. input terminals I,- I3, are used to bias T and T to a point where the loop gain is greater than unity and so initiate oscillation. Resistors R and R are of equal value and limit the base current of transistors T and T Diode D functions to provide a small initial forward bias. This forward bias decreases with an increase in the base-drive current, since the forward resistance of diode D drops when the current flowing therethrough increases.

Under overload conditions, the circuit is capable of oscillating with T and T out of bottoming when in the conducting state, in which case excessive power is dis sipated in the transistors as aforesaid. If the overload is such that the circuit ceases to oscillate, excessive power may still be dissipated by the transistors since they are biased on by the current through resistor R in the circuit of FIGURE 1, the two junction transistors T -T act as switches which are closed alternately so that the DC. input voltage from input terminals 1 -1 is applied to each of the primary windings (P P in turn. The transistors are switched on and oii alternately by feedback applied to'their base electrodes by feedback windings F F The windings P and F are on a common magnetic core and the same applies to the pair of windings P F Each pair may, if desired, be on a separate core, in which case each transformer unit has a secondary winding with the two secondaries connected in parallel to couple the cores and provide a common A.C. Wave. Preferably, however, all the windings P P F F are wound on a common core with a secondary winding S. The A.C. wave of the secondary winding may be used directly as the output of the circuit arrangement, or it may be rectified if it is desired to use the circuit as a DC. converter. An example of such an optional rectifying arrangement is shown in FIGURE 1 and comprises a bridge of rectifiers D connected to a load R shunted by a smoothing capacitor C FIGURE 2 shows the inverter section of the circuit of FIGURE 1 together with a monitor and protection circuit in accordance with the invention; and

FIG. 3 shows a variant of the circuit arrangement of FIG. 2.

The collector voltage of each of transistors T and T has a substantially square wave-form, and the monitor means are arranged to monitor only the level of the waveform correspondingto the conduction state i.e. the more positive level. A pair of rectifiers D D is used to provide a substantially smooth DC. voltage corresponding to the mean value of the said voltage level for operation of the protection means. The latter means include auxiliary transistors T -T each of which has its emittercollector path connected across the emitter-base path of one of the main or push-pull transistors.

The collectors of transistors T T are connected to point A via the rectifiers D -D the point A being on a potential divider circuit comprising resistors R -R R6R7 and leading to the base electrodes of transistors T T R and R7 have equal values.

The operation of the circuit is as follows. Assuming that the circuit is oscillating under normal load conditions, point A will be slightly negative with respect to earth, since it is held approximately at the bottoming voltage of transistor T or T At a time when transistor T is conducting and transistor T is cut ofi, point C will be negative and point D'positive with respect to earth. Since point D is positive with respect to point A, the collector diode of transistor T, will be in conduction and, by choosing appropriately the ratio of R to R point B may be made positive with respect to earth so that transistor T is cut off. Similar action occurs on the other half cycle with transistor T conducting.

On over-load, the output voltage will decrease. If, as a result, either transistor T or transistor T comes out of bottoming while in the conducting state, points A and B will both be negative and will cause transistors T and T to conduct, which increases the voltage drop across R and R and so reduces the base drive to transistors T and T The action is cumulative, since decrease in drive causes T and T to come further out of bottoming, and oscillation ceases and does not restart. The chain of resistors R R R and R, has a resistance such that transistors T and T are bottomed and thus hold the bases of transistors T and T at a low potential via a low impedance.

It is advantageous for the protection circuit to control the inverter transistors T -T in this manner for the following reason. When a very low impedance is placed across the emitter-base path of transistors T --T by bottoming of transistors T T transistors T -T 'are left with low collector currents only slightly greater than the cut-ofi current I In this collector-current region, and with their emitter-base voltage almost down to zero, transistors T T operate with a turn-over voltage which is materially greater than the turn-over voltage which would obtain if the protection circuit were to control transistors T -T by open-circuiting their emitter-base sections. This in turn permits higher supply voltages to be applied safely at terminals I -I and increases the efiiciencyof the circuit arrangements.

An asymmetric inverter circuit arrangement corresponding substantially to one half of the arrangement of FIG- of FIG. 2, a capacitor C of 25 uf. was connected between points B and I in order to facilitate starting of the oscillations. The sum of the resistances of resistors R and R was 1000 ohms and the action of the protection circuit was accordingly slowed down to some extent. This draw-back can however, be overcome by substituting the emitter-collector pathof a fifth transistor T for said starting capacitor, as shown on FIG. 3, the emitter being connected to point I and the base of said transistor being connected toits emitter through a resistor R andto point I by way of a capacitor C The fifth transistor thus, becomes conductive when switching on the circuitarrangement and remains conductive until its base capacitor has become charged through its basev resistor, thus facilitating starting of the oscillator, but it does not introduce-a time constant in the basecircuit of the transistors T andT and does not slow down the action of the protection circuit. 1

What is claimed is:

1. An inverter circuit arrangement comprising a pair of input terminals for connection to a direct voltage source, a pair of junction transistors each having base, emitter and collector electrodes, a feedback transformer having a pair of first winding portions arranged in balanced relationship with respect to each other and connected across said pair of input terminals, each in series with the collector-emitter path of one of said transistors, and a pair of second winding portions each connected across the base-emitter path of one of said transistors, each arranged in regenerative feedback relationship with respect to the first winding portion connected to the collector-emitter circuit of the same transistor, said tran sistors operating as a push-pull inverter producing output voltage pulses across said first winding portions and across a pair of output terminals coupled thereto for com nection to a load, monitoring means coupled to said pair of first winding portions for monitoring the level of the output voltage pulses, and overload protection means con nected across the base-emitter path of each transistor, said overload protection means operating in response to said monitoring means to reduce the forward base cur rent of each transistor when the level of said output voltage pulses falls below a predetermined level, said output voltage pulses having a substantially square wave= form and said monitoring means operating to monitor the level of said pulses corresponding only to the conduc' tive state of each transistor, said monitoring means cons prising a pair of rectifiers, one electrode of each rectifier being connected to the collector electrode of one tran= sistor respectively, and the other electrodes ofthe reedfiers being connected to a common point, said rectifiers supplying a substantially smooth direct voltage conesponding to the mean value of said output voltage pulses for operating said protection means. v

2. A circuit arrangement according to claim 1,- where in said overload protection means comprises a pair of auxiliary transistors each having collector, emitter and base electrodes, the collector-emitter path of each auxil iary transistor being connected across the base-emitter path of each junctiontransistor respectively, the base electrodes of the auxiliary transistors being coupled to said common point. I

3. An inverter circuit arrangement comprising a pair of input terminals connected to a direct voltage source, a junction transistor having base, emitter and collector electrodes, a feedback transformer having a first wind ing portion connected across said pair of input terminals in series with the collector-emitter path of said transistor, and a second Winding portion connected across the base emitter path of said transistor and arranged in regenera tive feedback relationship with respect to said first wind ing portion, said transistor operating as an inverter producing an output voltage across said first winding portion and across a pair of output terminals coupled thereto and adapted for connection to a load, monitoring means coupled to said' first winding portion for monitoring the level of the output voltage pulses corresponding only to the conductive state of the transistor, and overload protection means connected across the base-emitter path of said transistor, said overload protection means operating in response to said monitoring means to reduce the forward base current of the transistor when the level of said output voltage pulses falls below a predetermined 'value, said monitoring means comprising a rectifier having one electrode connected to said collector electrode and its other electrode resistively coupled to one of said input terminals, said other electrode supplying a direct voltage to said overload protection means, said direct j voltage having a mean value corresponding to the mean value of the output voltage pulses.

4. A circuit arrangement according to claim 3, wherein said overload protection means comprises an auxiliary t transistor having emitter, base and collector'electrodes,

J the emitter-collector path of the auxiliary transistor being connected across the base-emitter path of the junction transistor and the base electrode of the auxiliary transistor being coupled to said other electrode of the rectifier.

References Cited in the file of this patent UNITED STATES PATENTS 2,702,861 Wingate Feb. 22, 1955 6 Von De Polder Mar. 5, 1957 Light May 7, 1957 Woltf May 21, 1957 Light Sept. 30, 1958 Light Sept. 30, 1958 McMurren Feb. 17, 1959 Humez et al. Aug. 23, 1960 

